For years, digital electronics has been dominated by Si/SiO2 based technology, because of the low cost of silicon and the properties (structural and electronic) of the Si/SiO2 system. Since new applications are focused on wireless and optical communication, conventional silicon based devices do not offer any more sufficient high frequency and opto-electronic properties. Nowadays, two materials/systems have the functionality required for these new applications: III-V materials (InP, GaAs, and the like) and IV-IV heterostructures (SiGe/Si).
Until now high frequency and optical applications mostly have been outclassed by the III-V materials grown on GaAs wafer, but the lack of natural oxide such as SiO2 and the low level of integration possible on these wafers are major drawbacks.
SiGe/Si heterostructures comprising a strain adjusted SiGe layer and a strained Silicon layer improve the electron transport into the strained silicon channel, thanks to a band offset at the heterointerface between SiGe and Si, which leads to the confinement of the electrons in a quantum well. The modification of the band structure is due to the lattice mismatch between Si and SiGe.
In order to benefit from both the functionality of these new systems and the advantages of silicon technology (low cost, high throughput and capacities), one solution is to integrate III-V compounds or SiGe/Si on Si substrate. The main challenge is then to deposit these materials on a substrate, which has a different lattice parameter. The lattice mismatch between the film and the substrate gives rise to the formation and the propagation of dislocations into the epilayer. Each dislocation in the active part of the epitaxial layer leads to the deterioration of the electronic properties and of the carrier transport due to scattering.
The density of dislocations rising to the top of the epitaxial layer can be as high as 1E11 cm−2 for SiGe and 1E10 cm−2 for GaAs, which is too high for any application. In order to grow high functionality materials it is necessary to keep the dislocation density in the active part of the epitaxial layer as low as possible and preferably below 1E4 cm−2, although this specification is not well established yet.
One solution to grow SiGe and III-V compounds on top of a Si substrate without any defects is to insert a Strain Relaxed SiGe Buffer (SRB) between substrate and hetero-system. The characteristics of SiGe make it a suitable compound for SRB application. Furthermore it is possible on Si substrates to adapt SiGe layer systems with 0 (pure Si) to 4.16% (100% Ge) lattice mismatch, determined by the Ge content in the SRB.
Although rather high electron mobility and low threading dislocation density can be obtained, thick graded buffers still present some major economical and technological drawbacks: growth time, material consumption, too large step height for integration with Si microelectronics. To overcome these problems, many efforts have been carried out on Thin Strain Relaxed Buffer (TSRB).
An epitaxial layer can only relax over a critical thickness by introducing dislocations into the epitaxial layer. This critical thickness is mainly determined by the growth conditions (growth rate, temperature, and the like) and by the defects present in the epilayer and/or at the heterointerface. The TSRB employs defects in order to reduce this critical thickness and to confine the dislocations at the heterointerface.
There are three main methods to do this, namely in situ defect creation, ex situ defect creation and compliant substrate. In the preferred embodiments, the in-situ method is used, in which grown-in point defects can act as nucleation sites for misfit dislocations and significantly reduce the critical thickness. The principle of this method is to grow the defects during the deposition of the SRB.
Several researchers have been working on this type of SRB, by using Molecular Beam Epitaxy (MBE), Ultra High Vacuum Chemical Vapor Deposition (UHV-CVD) or Low-Energy Plasma Enhanced Chemical Vapor Deposition (LEPECVD). These methods lead to a high degree of relaxation for the top layer (>90%) for very low thickness (200 nm), while the dislocations are confined into the low temperature epilayer.
The main drawback of these methods is that they are only applicable for MBE, UHV-CVD, or LEPECVD systems. As in RPCVD systems, the growth rate is strongly linked to the growth temperature; the growth at ultra low temperature would be very slow or even impossible.
PCT International Application WO01/73827 by Matsushita describes how an annealed SiGeC crystal layer, comprising a matrix SiGeC crystal layer relaxed in lattice and almost free from dislocations and SiC microcrystals dispersed in the layer, is formed on a Si substrate by heat-annealing a SiGeC crystal layer-deposited Si substrate. Then, a Si crystal layer is deposited on an annealed SiGeC crystal layer to form a distorted Si crystal layer with a minimum dislocation. The main differences with the solution presented by the preferred embodiments lie in the different principle of threading dislocation reduction used and in the degree of relaxation reached.
Osten et al. (‘Relaxed Si1-xGex/Si1-x-yGexCy buffer structures with low threading dislocation density’, Appl. Phys. Lett. 70(21), 26 May 1997, pp. 2813-2815) make strain relaxed buffers by deposition of thick SiGe and SiGeC layers. This method is a modification of the standard thick buffer with step-graded Ge-content. Here, layer relaxation is initiated by the high internal stress. This internal stress is build up by growing above a temperature dependent metastable critical layer thickness. Substitutional carbon is used to match the lattice constant of the Si1-x-yGexCy with the underlying Si1-zGez layer (x>z) and to avoid threading dislocations reaching the surface, as dislocation glide is retarded in the SiGeC layer. The use of substitutional carbon sets an upper limit to the carbon content. Above this limit, interstitial carbon would be implemented.
Lanzerotti et al. (‘Suppression of boron outdiffusion in SiGe HBTs by carbon incorporation’, International Electron Devices Meeting (IEDM) 96, 8-11 Dec. 1996, pp. 249-252 (IEEE, New York, 1996)) disclose a HBT device with a base consisting of a SiGe/SiGeC/SiGe layer stack, which consequently should be free of any defects. The Ge is implemented to reduce the transit time from emitter to collector, while substitutional C is used to reduce boron outdiffusion in the base. Because the total layer stack has to be defect free, substitutional carbon is required, which set an upper limit to the carbon concentration. The Si cap layer is fully relaxed, because it was grown on strained SiGe. This layer stack is certainly not used as SRB. SRB's allow depositing a strained Si layer with a Ge rich strained SiGe or a III/IV layer on top of it. This is implemented in lateral devices to enhance carrier mobility. Defects are inherent to the SRB fabrication process. The SRB may not be part of the active device area. In this paper the total thickness of the SiGe/SiGeC/SiGe layer stack should stay below the critical thickness for layer relaxation. In contradiction, SRB layers have to be thick enough to enable relaxation.